Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies

ABSTRACT

Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

BACKGROUND

[0001] 1. Technical Field

[0002] The present invention relates to sensing circuitry for readingand verifying the contents of electrically programmable and erasablenon-volatile memory cells, useful in low-supply-voltage technologies.

[0003] Specifically, the invention relates to sensing circuitry forreading and verifying the contents of electrically programmable anderasable non-volatile memory cells, said sensing circuitry comprising asense amplifier having a first sensing-circuit portion connected to acell to be read and a second reference-load-circuit portion connected toa reference generator.

[0004] The invention relates, particularly but not exclusively, tocircuitry for sensing the state of memory cells in embedded applicationswith low supply voltages, this description making reference to thatfield of application for convenience of illustration only.

[0005] 2. Prior Art

[0006] As is well known, semiconductor memories are organized in cellarrays set up as rows or wordlines and columns or bitlines.

[0007] Each cell has essentially a floating-gate transistor, which alsohas drain and source terminals. The floating gate is formed on top of asemiconductor substrate and separated from the substrate by a thin layerof gate oxide. A control gate is coupled capacitively to the floatinggate through a dielectric layer, and metal electrodes are provided tocontact the drain, source, and control gate so that predeterminedvoltage values can be applied the memory cell.

[0008] The cells in one wordline share an electric line driving theirrespective control gates (directly in flash memories, and indirectlythrough a pass transistor in EEPROMs), while the cells in one bitlinehave the drain terminal in common.

[0009] The state of the cell is sensed, i.e. the information stored init is “read”, by means of sensing circuitry.

[0010] The reading is effected by sensing a current value that flowsthrough a cell to be read, at a preset bias through an amplifyingcircuit, in particular a sense amplifier.

[0011] The sense amplifier is used to bias the cell drain terminal, aswell as to read the cell state. The drain terminal is accessed throughthe bitline, which is, as mentioned before, a metal line interconnecting(directly in flash memories, and indirectly through a select transistorin EEPROMs) the drain terminals of all the cells in one column of thearray. Thus, the bitline has an amount of capacitance that isproportionate to the vertical dimension of the array and must beprecharged at the voltage level to which the drain terminal of a cellbeing read is to be biased. The precharging is also performed throughthe sense amplifier.

[0012] Recent generations of memories are designed to provide shorteraccess times along with larger storage capacities (i.e., number ofcells) with supply voltages that are specified at ever lower levels.

[0013] Accordingly, faster sense amplifiers at low supply voltages arein demand.

[0014] A first prior approach to satisfy this demand is illustrated by aconventional sense amplifier SA1 for use in smart card applications, asshown in FIG. 1.

[0015] In particular, the sense amplifier SA1 has a first circuitportion or sensing portion 1 connected between a voltage supply Vdd andground GND.

[0016] The sensing portion 1 has a first leg, comprising a cascade of aPMOS transistor Mmir10 and an NMOS transistor M10. The sensing portion 1also has a second leg 3 comprising a native transistor NAT1, which is alow-threshold transistor connected between the voltage supply Vdd and afirst node A.

[0017] The control terminal of the native transistor NAT1 is connectedto an interconnection node MAT, itself connecting the transistors Mmir10and M10 together. The control terminal of transistor M10 is connected tothe node A. A resistor R is connected between the node A and a nodeBUS1.

[0018] This node BUS1 is connected, through a decode circuit N1, to thedrain terminal of a cell 4 whose state is to be sensed.

[0019] At steady state, the current flowing through the cell 4 alsoflows through the transistor NAT1. Since the voltage level at node A isdependent on the size of transistor M10 and the bias current totransistor NAT1, the node MAT is brought to a level such that a voltageVGS (VMAT-VA) at transistor NAT1 will cause a current I flowing throughthe transistor M10 to equal the current ICELL1 flowing through the cell4. Therefore, transistor NAT1 effects a current-to-voltage conversion.

[0020] The sense amplifier SA1 further comprises a second circuitportion, or reference portion 5, connected between the voltage supplyand ground GND. The reference portion 5 has a first leg 7 comprising acascade of a PMOS transistor Mmir20 and an NMOS transistor M2. Thereference portion 5 also has a second leg 6 comprising a nativetransistor NAT2 connected between the voltage supply Vdd and a node B.

[0021] The control terminal of the native transistor NAT2 is connectedto a node REF2, itself connecting the transistors Mmir20 and M2together. The control terminal of transistor M2 is connected to the nodeB, which also has a reference cell 8 connected to it.

[0022] This reference portion 5 performs dynamically like the firstsensing portion 1. The transistor NAT2 effects then a current-to-voltageconversion, with the voltage level at node REF2 being set by a givenreference current IREF2.

[0023] If more current flows through the cell 4 to be read than throughthe reference cell 8, then node MAT is at a higher voltage level thannode REF2, whereas if the current through the cell 4 to be read issmaller than the current through the reference cell 8, then node MAT isbrought at steady state down to a lower voltage level than node REF2.

[0024] By comparing these two nodes, MAT and REF2, in a voltagecomparator (not shown because conventional) the state of the cell 4 canbe determined, the state of the reference cell 8 being known beforehand.

[0025] While being advantageous in several aspects, this first approachhas shortcomings. The voltage difference between the voltage supply Vddand ground GND is equal to the sum of the voltage Vds at PMOS Mmir10,voltage Vgs at the native (low-threshold) transistor NAT1, and voltageVgs at the inverter M10, namely:

Vdd=VdsMmir 10+VgsNAT 1+VgsM 10  (1)

[0026] Equation (1) above becomes a fairly critical one with low supplyvoltages.

[0027] Another shortcoming comes from the bound placed on the size oftransistors M10 and NAT1. Transistor M10, in fact, cannot be highlyconductive because the bitline bias is dependent on its voltage Vgs.

[0028] As best seen with reference to FIG. 2, however, the I-Vcharacteristics of MOS transistors diverge from each other astemperature varies, except around a specific value of the voltage Vgs.This value of Vgs is the value at which temperature compensation isachieved between the effects of diminishing threshold as temperatureincreases (that depresses Vgs) and diminishing current gain (thatincreases the voltage Vgs for a given bias current 1).

[0029] Nor can transistor M10 deviate substantially from that value ofthe voltage Vgs. For example, it may be about 740 mV, to prevent thebitline bias from changing substantially with temperature.

[0030] Transistor NAT1 cannot be highly conductive because thesensitivity S of the sense amplifier is dependent on it, as follows:

S=|dVMAT/dlCELL 1|=1/gmNAT 1  (2)

[0031] where,

[0032] VMAT is the voltage at node MAT;

[0033] ICELL1 is the current through the cell 4 to be read; and

[0034] gmBAT1 is the transconductance of the native transistor NAT1.

[0035] For instance, assuming the circuit of FIG. 1 to have beendimensioned for sensitivity S≧25 mV/uA and the voltage difference atnode BUS1 (ΔVbus1)≦60 mV at varying temperatures between −40° and 125°C., a current ICELL1=3 uA is sufficient to bring the node MAT to about1.1V, as shown in FIG. 3, and at Vdd=1.2V, the PMOS transistor Mmir10has Vds=100 mV and its mirrored current I goes to 7.3 uA, from 8 uA, asshown in FIG. 4.

[0036] The sensing circuit SA1 is also used to precharge the bitline.Nodes MAT and REF are preset at the supply voltage Vdd and the groundvoltage GND, respectively. At power-on of the sensing circuit SA1, nodeBUS1 is discharged, i.e. is same as GND, and the voltage Vgs at thenative transistor NAT1 is initially same as Vdd. At this stage,transistor NAT1 allows the bitline to be precharged with much overdriveand, therefore, a large current ICELL1. BUS1, while under charge, willtend toward the bias voltage set by transistor M10 functioning as aninverter, and by its bias current I. Node MAT is then brought to asufficient level for the current needed by the cell 4 to be read to flowthrough transistor NAT1.

[0037] Therefore, a need has arisen for a sensing circuit that can beoperated on low supply voltages and that overcomes problems that besetsprior-art sensing circuits.

SUMMARY OF THE INVENTION

[0038] In one aspect of the invention, sensing circuitry includes twocurrent/voltage conversion blocks respectively connected to a memorycell to be read and to a reference cell, said blocks being connected toa single bias and precharge block such that the bias block is not in theconductive path between the voltage supply Vdd and ground GND of theindividual conversion blocks.

[0039] Features and advantages of the sensing circuit according to theinvention will be apparent from the following description of anembodiment thereof, given by way of non-limitative example withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In the drawings:

[0041]FIG. 1 is a diagram of a sense-amplifier read circuit according tothe prior art;

[0042]FIG. 2 is a plot of the current vs. voltage characteristics of MOStransistors at different temperatures;

[0043]FIG. 3 is a plot of the voltages at two nodes of thesense-amplifier read circuit of FIG. 1;

[0044]FIG. 4 is a plot of a bias current of the sense-amplifier readcircuit of FIG. 1;

[0045]FIG. 5 is a block diagram of sensing circuitry according to anembodiment of the invention; and

[0046]FIG. 6 is a schematic diagram of the sensing circuitry of FIG. 5.

DETAILED DESCRIPTION

[0047] With reference to the drawings, in particular to FIG. 5 thereof,sensing circuitry for reading and verifying the contents of electricallyprogrammable and erasable non-volatile memory cells, adapted for use inlow supply voltage technologies, is shown generally at 10 according toan embodiment of the invention.

[0048] The sensing circuitry 10 comprises a sense amplifier 11 of thedifferential type, employed to compare a current ICELL that flowsthrough a cell 12 in a memory array with a reference current generatedby a reference generator IREF. The reference current from the referencegenerator IREF is the current that flows through a reference cell 13,e.g. a virgin cell, or is generated by a dedicated current-generatingcircuit.

[0049] The sense amplifier 11 uses two current-to-voltage (I/V)conversion blocks S1 and S2 to convert read analog data, i.e. thecurrent values being read, to digital data.

[0050] More particularly, the circuitry 10 comprises first and secondI/V conversion blocks S1 and S2 that are connected between a firstvoltage reference, e.g. the voltage supply Vdd, and a second voltagereference, e.g. ground GND. The blocks, S1 and S2, generate first andsecond voltages VBUS and VOUT1 for comparison in a comparator 14.

[0051] According to an embodiment of the invention, a single bias andprecharge block 15 supplies a bias current IPOL and a precharge currentIPRECH to both blocks S1 and S2.

[0052] An embodiment of the sensing circuitry 10 according to theinvention will now be described in greater detail with reference to FIG.6.

[0053] Block S1 comprises a first transistor Mmir2, which has itsconduction terminals connected between the voltage supply Vdd and afirst node BUS. A second transistor M1 has its conduction terminalsconnected between this node BUS and ground GND.

[0054] In a preferred embodiment, the second transistor M1 comprises twotransistors M1 a and M1 b connected in parallel in a diodeconfiguration. The cell 12 to be read is also connected to the node BUS.

[0055] The second block S2 comprises a first transistor Mmir3 having itsconduction terminals connected between the voltage supply Vdd and afirst node OUT. A second transistor M2, which may be an NMOS transistor,has its conduction terminals connected between the node OUT and groundGND.

[0056] In a preferred embodiment, the second transistor M2 in the blockS2 may advantageously comprise two transistors M2 a and M2 b connectedin parallel, with transistor M2 a provided in a diode configuration. Thecontrol terminal of transistor M2 b is then connected to node BUS.

[0057] The control terminals of transistor Mmir2 and transistor Mmir3are connected together and to the bias and precharge block 15.

[0058] Advantageously, these transistors Mmir2 and Mmir3 are PMOStransistors, whereas transistors M1 and M2 are NMOS transistors.

[0059] It should be noted that the blocks S1 and S2 of this inventionuse no bias transistor comparable to the transistors NAT1 and NAT2 ofprior circuits. In this way, their path GATE-SOURCE, and hence thevoltage VGS, can be removed from the path between the voltage supply Vddand ground GND.

[0060] The bias and precharge block 15 includes a circuit that deliversthe reference voltage VPOL to the P-channel transistors Mmir2 and Mmir3,in order to they deliver the precharge current to node BUS.

[0061] In particular, the bias and precharge block 15 is connectedbetween the voltage supply Vdd and ground GND, and has a first leg 16,which comprises a cascade of a transistor Mmir1 in diode configurationand a transistor M6. Transistor Mmir1 forms a current mirrorconfiguration with the transistors Mmir2 and Mmir3 of blocks S1 and S2.

[0062] The bias and precharge block 15 has, moreover, a second leg 17,which comprises a cascade of a transistor Mmir0 and transistors M4 andM5. The control terminals of transistors M4 and M5 are connectedtogether. The control terminal of transistor Mmir0 is driven by areference voltage VIPSENSE.

[0063] Transistor M6 has its control terminal connected via a commonnode A to transistors Mmir0 and M5.

[0064] Advantageously, transistors Mmir0 and Mmir1 also form a currentmirror.

[0065] The bias and precharge block 15 further comprises a transistor M3connected between the shared node by transistors M4, M5 and ground GND.The control terminal of transistor M3 is then connected, via a nodeFEEDBACK, to the control terminal of the transistor M1 in the firstblock S1.

[0066] Advantageously, transistors Mmir0 and Mmir1 are PMOS transistors,whereas transistors M3, M4, M5 and M6 are NMOS transistors.

[0067] Advantageously in this embodiment of the invention, the twoblocks S1 and S2 are such that nodes BUS and OUT will be at the samevoltage level when the currents ICELL and IREF, respectively, that flowsthrough the cell 12 to be read and the reference cell 13, are the same.

[0068] Since at steady state, transistor M3 shorts out the voltage Vdsof transistor M4, transistors Mmir1 and Mmir2 will be mirroring acurrent IPOL, given as:

IPOL=I*(W/L)_(M6)/(W/L)_(M5)  (3)

[0069] where,

[0070] I is the current input to node A;

[0071] (W/L)_(M6) is the channel aspect ratio e of transistor M6; and

[0072] (W/L)_(M5) is the channel aspect ratio e of transistor M5.

[0073] A current IM1 flowing through transistor M1, comprised oftransistors M1 a and M1 b in parallel, for example, is:

IM 1=IPOL−ICELL  (4)

[0074] where,

[0075] IPOL is the bias current of blocks S1 and S2; and

[0076] ICELL is the current flowing through the cell 12 to be read.

[0077] The voltage VBUS at node BUS is proportional, except for thethreshold voltage of transistor M1, to the current IM1. Thus, the largercurrent ICELL, the lower will be the voltage level VBUS at node BUS,according to Relation (4) above, and the higher the voltage level VOUTat node OUT.

[0078] By having the voltages at nodes BUS and OUT compared in thevoltage comparator 14, the state of the cell 12 to be read can bedetermined.

[0079] Advantageously, the comparator 14, shown in FIG. 6, used for thecomparison does not degrade the performance of the low-voltage sensingcircuit 10, since comparator 14 is a similar construction to the INconversion blocks S1 and S2.

[0080] In particular, the comparator 14 is connected between the voltagesupply Vdd and ground GND, and comprises: a current mirror formed oftransistors Mmir7 and Mmir8, with transistor Mmir7 in a diodeconfiguration. Each one of the transistors Mmir7 and Mmir8 in the mirrorhas a transistor M10 and M11 respectively connected in series therewith.

[0081] The control terminal of transistor M10 is then connected to nodeOUT, while the control terminal of transistor M11 is connected to nodeBUS.

[0082] Advantageously, transistors Mmir7 and Mmir8 are PMOS transistors,and transistors M10 and M11 are NMOS transistors.

[0083] To have a minimum of sensing errors caused by comparator 14, agood match of blocks S1 and S2 must be achieved. This is done by havingthe transistors M10, M11, M1 and M2 all of the same size.

[0084] This also provides good control of power usage, because thecurrent forced on blocks S1 and S2 of the sense amplifier 11 is at mostpassed through the transistors Mmir7 and Mmir8 of comparator 14.

[0085] How the signals evolve dynamically will now be described.

[0086] Nodes BUS and OUT are preset at the supply voltage Vdd and theground voltage GND, respectively. At power-on of the sense amplifier 11,these nodes BUS and OUT are released, transistor M3 is turned off, andthe mirrored current by transistor Mmir1 becomes:

IPRECH+IPOL=I(W/L)_(M6)(1/(W/L))_(M4)+1/(W/L)_(M5))  (5)

[0087] with,

IPRECH=I(W/L)_(M6)/(W/L)_(M4)  (6)

[0088] where,

[0089] I is the input current to node A;

[0090] (W/L)_(M6) is the channel aspect ratio of transistor M6;

[0091] (W/L)_(M4) is the channel aspect ratio of transistor M4; and

[0092] IPOL is as given by Relation (3).

[0093] The capacitance associated with the bitline that is connected tothe drain of the cell 12 to be read is precharged quite rapidly by meansof the current IPRECH added.

[0094] Upon the bitline reaching a level at which transistor M3 isturned on, transistor M3 shorts out transistor M4, and the mirroredcurrent in transistor Mmir1 is again IPOL, according to Relation (3)above.

[0095] The more resistive the transistor M4, the larger the currentIPRECH and the faster is the bitline charged.

[0096] On the other hand, if transistor M4 is made too resistive, thevoltage level at node A could reach a value such that transistor Mmir0will move into the linear range and no longer mirror the input current Ito node A correctly.

[0097] Advantageously in a modification of the sensing circuitry 10according to an embodiment of the invention, the sense amplifier 11further comprises an auxiliary precharge block 18.

[0098] The auxiliary precharge block 18 delivers a precharge boostcurrent IAUX.

[0099] In particular, the auxiliary precharging circuit 18 is connectedbetween the voltage supply Vdd and ground GND, and comprises a currentmirror formed of the PMOS transistors Mmir5 and Mmir6, of whichtransistor Mmir5 is a diode configuration, and a transistor M9 connectedin series with transistor Mmir5.

[0100] The auxiliary precharging circuit 18 has also a leg comprising atransistor Mmir4 in cascade with a diode-configured transistor M8. Theauxiliary precharging circuit 18 additionally comprises a transistor M7connected in parallel with transistor M8.

[0101] The control terminal of transistor M7 and the conduction terminalof transistor Mmir6 are connected to each other and to node FEEDBACK.

[0102] Advantageously, transistors Mmir4, Mmir5 and Mmir6 are PMOStransistors, and transistors M7, M8 and M9 are NMOS transistors.

[0103] The auxiliary precharging circuit 18 is dimensioned, for example,to deliver a current only during the precharging step. The moreconductive transistor M7, the sooner is the auxiliary precharging stepcompleted. The precharge current IAUX is set in particular by the ratiosof the current mirrors formed of the PMOS transistors Mmir5 and Mmir6.

[0104] Note should be taken of that this auxiliary precharging step iscompleted ahead of the sensing step, to avoid overshooting at the nodeBUS.

[0105] The sensing circuitry 10 is suitable to form, for example, asense amplifier 11 capable of discriminating between the states of cellsin an embedded EEPROM macrocell for applications SMARTCARD with abitline capacitance of about 1 pF, supply voltages of down to 1.2 V orless, and a sensing time of less than 20 ns. Within this time range, thebitline would be precharged and the state of the cells with a supplyvoltage of 1.2 to 1.9 V determined.

[0106] To summarize, the sensing circuitry provides a circuit structurethat is fully compatible with standard processes and enablesdiscriminating between small current differences, e.g. differences ofabout 1 uA.

1. A circuit for reading a memory cell, the circuit comprising: a readnode operable to receive a read current from the memory cell; a firstcurrent source operable to provide a first bias current to the readnode; a first transistor having a control terminal and a firstconduction terminal coupled to the read node; a reference node; areference generator operable to provide a reference current to thereference node; a second current source operable to provide a secondbias current to the reference node; and a second transistor having acontrol terminal coupled to the read node and having a first conductionterminal coupled to the reference node.
 2. The circuit of claim 1,further comprising: first and second supply nodes; wherein the first andsecond current sources are coupled to the first supply node; and whereinthe first and second transistors each have a respective secondconduction terminal coupled to the second supply node.
 3. The circuit ofclaim 1 wherein the first bias current equals the second bias current.4. The circuit of claim 1 wherein: the first and second current sourceseach comprise a respective PMOS transistor; and the first and secondtransistors each comprise a respective NMOS transistor.
 5. The circuitof claim 1, further comprising: a third transistor having a controlterminal and a conduction terminal coupled to the read node; and afourth transistor having a control terminal and a conduction terminalcoupled to the reference node.
 6. The circuit of claim 1, furthercomprising: a bias generator operable to generate a bias voltage; andwherein the first and second current sources are operable to generatethe first and second bias currents in response to the bias voltage. 7.The circuit of claim 1, further comprising a comparator having first andsecond input terminals respectively coupled to the read and referencenodes.
 8. The circuit of claim 1, further comprising a prechargercoupled to the read node.
 9. A method for reading a memory cell, themethod comprising: sourcing a first bias current to a read node; sinkinga read current from the read node; sinking from the read node a firstdifference current that is inversely proportional to the read current;sourcing a second bias current to a reference node; sinking a referencecurrent from the read node; and sinking from the reference node a seconddifference current that is inversely proportional to the read current.10. The method of claim 9 wherein the first bias current equals thesecond bias current.
 11. The method of claim 9, further comprisingcomparing a voltage on the read node to a voltage on the reference nodeto determine a data value stored in the memory cell.
 12. The method ofclaim 9, further comprising sinking from the read node a thirddifference current that is inversely proportional to the read current.13. The method of claim 9, further comprising sinking from the referencenode a third difference current that is proportional to the readcurrent.
 14. Sensing circuitry for reading and verifying the contents ofelectrically programmable and erasable non-volatile memory cells, whichcircuitry comprises a sense amplifier having a first sensing circuitportion connected to a cell to be read and provided with an outputterminal for connection to a first input terminal of a comparator, andhaving a second reference circuit portion connected to a referencecurrent generator and provided with an output terminal for connection toa second input terminal of said comparator, characterized in that saidfirst and said second circuit portions comprise a series of first andsecond transistors, respectively, being connected between a firstvoltage reference and a second voltage reference and having respectivepoints of interconnection taken to said output terminals of said firstand second circuit portions.
 15. Sensing circuitry according to claim14, characterized in that said second transistor in said second circuitportion comprises a parallel of third and fourth transistors, thecontrol terminal of said fourth transistor being connected to saidoutput terminal of said first circuit portion.
 16. Sensing circuitryaccording to claim 14, characterized in that it comprises a bias andprecharge block connected between a first voltage reference and a secondvoltage reference, as well as connected to control terminals of saidfirst transistors in said first and second circuit portions and to thecontrol terminal of said second transistor in said first circuitportion.
 17. Sensing circuitry according to claim 14, characterized inthat said first transistors in said first and second circuit portionsare PMOS transistors, and said second transistors in said first andsecond circuit portions are NMOS transistors.
 18. Sensing circuitryaccording to claim 14, characterized in that said second transistor insaid first circuit portion comprises a pair of transistors, beingconnected in parallel with each other in a diode configuration andhaving control terminals connected to said output terminal of said firstcircuit portion.
 19. Sensing circuitry according to claim 16,characterized in that said first transistors in said first and secondcircuit portions have interconnected control terminals.
 20. Sensingcircuitry according to claim 19, characterized in that said bias blockhas a first leg and a second leg, with said first leg comprising acascade of a first transistor in a diode configuration and a secondtransistor, and said second leg comprising a cascade of a firsttransistor and a second transistor, the control terminal of said secondtransistor in said first leg being connected to a shared node of saidfirst transistor and second transistor in said second leg.
 21. Sensingcircuitry according to claim 20, characterized in that said firsttransistor in said first leg forms a current mirror configuration withthe first transistors in said first and second circuit portions. 22.Sensing circuitry according to claim 20, characterized in that saidfirst transistor in said first leg and said first transistor in saidsecond leg form a current mirror.
 23. Sensing circuitry according toclaim 20, characterized in that said second transistor in said secondleg is a cascade of third and fourth transistors, said second legfurther comprising a fifth transistor connected between a shared node ofsaid third and fourth transistors and said second voltage reference,said fifth transistor having a control terminal connected to a controlterminal of said second transistor in said first circuit portion. 24.Sensing circuitry according to claim 14, characterized in that saidcomparator includes a current mirror formed of first and secondtransistors, with said first transistor being a diode configuration. 25.Sensing circuitry according to claim 24, characterized in that saidfirst transistor of said comparator is connected in series with a thirdtransistor, and that said second transistor of said comparator isconnected in series with a fourth transistor, said third transistorhaving a control terminal connected to the node, and said transistorhaving a control terminal connected to said node).
 26. Sensing circuitryaccording to claim 25, characterized in that said third transistor andfourth transistor of said comparator, and said second transistor in saidfirst circuit portion and said second transistor in said second circuitportion, are all the same size.
 27. Sensing circuitry according to claim16, characterized in that it comprises an auxiliary precharge circuitconnected between said first and said second voltage reference, saidauxiliary precharge circuit including a current mirror formed of firstand second transistors, with said first transistor being a diode aconfiguration, said auxiliary precharge circuit further including athird transistor connected in series with said first transistor, thesecond transistor being connected to said first node.
 28. Sensingcircuitry according to claim 27, characterized in that said auxiliaryprecharge circuit also has a leg comprising a first transistor connectedin cascade with a second transistor, the latter in a diodeconfiguration, and comprising a third transistor connected in parallelwith said transistor, a control terminal of said third transistor and acontrol terminal of said second transistor of said mirror in saidauxiliary precharge circuit being connected together.